suppliers of SY10EL38LZC and PDF data of SY10EL38LZC

LGATE (Pin l) Connect the LGATE pin to the gate of lower MOSFET. This pin provides the gate drive for the lower MOSFET. PGND/GND (Pin 2, 3) Signal and power ground for the lC. All voltage levels are measured with respect to this pin. VCC (Pin 4) This is the main bias supply for the RT9205/A. This pin also provides the gate bias charge for the gate of lower MOSFET. The voltage at this pin is monitored for ensuring a proper power-on reset (POR). This pin is also the out of an internal 6.OV regulator that powered from the BOOT pin when the BOOT pin is directly powered from ATX 12V. DRV (Pin 5) This pin is the output of a linear controller. It should be connected to the base of an external bypass NPN transistor or the gate of a N-MOSFET to form a linear low dropout regulator. FBL (Pin 6) This pin is connected to the output resistor-divider of an external power transistor or a N-MOSFET based low dropout regulator for regulating and monitoring the output voltage. This pin is also connected to the protection monitor and the invertering input of error amplifier of internal linear regulator inside the lC. FB (Pin 9) This pin is connected to the PWM converter's output - divider for regulating and monitoring the output voltage of buck converter. This pin also connects to the protection monitor and the inverting input of internal PWM error amplifier inside the lC. BOOT (Pin 13) This pin provides ground referenced bias voltage to the upper MOSFET driver. A bootstrap circuit is used to create a voltage that is suitable for driving a logic-level N-channel MOSFET when operating at a single 5V power supply. This pin also could be powered from ATX 12V, in this situation, an internal 6.OV regulator will supply to VCC pin for generating bias required inside the lC.
SY10EL38LZC Price