SY10EP05VKITR Datasheet| Items | Symbols | Conditions | Max | Units | | Forward Voltage Drop | VFM | IF - 4A | 0.55 | V | | Reverse Current | IRRM | VR= VRRM | 5 | mA | | Thermal Resistance | Rthc | · Junction to case | 3O | /w | | | | | |
SY10EP05VKITR Price Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to fullload while observing the output for any oscillations. If no oscil- lations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature. Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage conditions. Step 5: If the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. A smaller capacitor will usually cost less and occupy less board space. If the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger stan- dard capacitor value. Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real working enwronment. Vary the ESR to reduce ringing. Step 7: Remove the unit from the environmental chamber and heat the IC with a heat gun. Vary the load current as instructed in step 5 to test for any oscillations. Once the mimmum capacitor value with the maximum ESR is found, a safety factor should be added to allow for the tolerance of the iapacitor and any variations in regula- tor performance. Most good quality aluminum electrolytic capacitors have a tolerance of +207 so the minimum value found should be increased by at least 50'/o to allow for this tolerance plus the variation~hich will occur at low tem- peratures. The ESR of the capacitor should be less than 50'70 0f the maximum allowable ESR found in step 3 above. SY10EP05VKITR on stock| Common-Source Amplifier Power Gain (VDD = 28 Vdc, Pout = 23 W Avg., IDO = 1050 mA, fl = 2112.5 MHz, f2 = 2122.5 MHz and fl = 2157.5 MHz, f2 = 2167.5 MHz) | Gps | 12.5 | 13.5 | | dB | | Drain Efficiency (VDD = 28 Vdc, Pout = 23 W Avg., IDO = 1050 mA, fl = 2112.5 MHz, f2 = 2122.5 MHz and fl = 2157.5 MHz, f2 = 2167.5 MHz) | 11 | 24 | 26 | | % | | Third Order Intermodulation Distortion (VDD = 28 Vdc, Pout = 23 W Avg., IDO = 1050 mA, fl = 2112.5 MHz, f2 = 2122.5 MHz and fl = 2157.5 MHz, f2 = 2167.5 MHz; IM3 measured over 3.84 MHz BW at fl -10 MHz and f2 +10 MHz referenced to carrier channel power.) | IM3 | | -37 | -35 | dBc | | Adjacent Channel Power Ratio (VDD = 28 Vdc, Pout = 23 W Avg., IDO = 1050 mA, fl = 2112.5 MHz, f2 = 2122.5 MHz and fl = 2157.5 MHz, f2 = 2167.5 MHz; ACPR measured over 3.84 MHz at fl -5 MHz and f2 +5 MHz.) | ACPR | | - 40 | -38 | dBc | | Input Return Loss (VDD = 28 Vdc, Pout = 23 W Avg., IDO = 1050 mA, fl = 2112.5 MHz, f2 = 2122.5 MHz and fl = 2157.5 MHz, f2 = 2167.5 MHz) | IRL | | -16 | -9 | dB | | | | | | |
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