SY10H601JCTR Datasheet| | JIj | | | | | | | | | i/IPu's, | | | Lvz | | | | | | yR'petiliie | | | I | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
SY10H601JCTR Price| Pin No. | Symbol | Description | | LQFP (X16/X18) | LQFP (X32/X36) | | 37 36 35,34,33,32, 100,99,82,81, 44,45,46,47, 48,49,50 80 | 37 36 35,34,33,32, 100,99,82,81, 44,45,46,47, 48,49,50 | AO A1 A2 - A16 A17 | Synchronous Address Inputs : These inputs are registered and must meet the setup and hold times around the rising edge of CLK. Pins 83 and 84 are reserved as address bits for higher-density 9Mb and 18Mb DBA SRAMs, respectively. AO and Al are the two lest significant bits (LSB) of the address field and set the internal burst counter if burst is desired. | | 93 (BW ) 94 (BW2) | 93 (BW ) 94 (BW2) 95 (BW3) 96 (BW4) | BW2 BW3 BW4 | Synchronous Byte Write Enables : These active low inputs allow individual bytes to be written when a WRITE cycle is active and must meet the setup and hold times around the rising edge of CLK. BYTE WRITEs need to be asserted on the same cycle as the address, BWs are associated with addresses and apply to subsequent data. BWl controls l/Oa pins; BW2 controls l/Ob pins; BW3 controls l/Oc pins; BW4controls l/Od pins. | | 89 | 89 | CLK | Clock : This signal registers the address, data, chip enables, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. | | 98 | 98 | CE | Synchronous Chip Enable : This active low input is used to enable the device. This input is sampled only when a new external address is loaded (ADV/LD LOW). | | 92 | 92 | CE2 | Synchronous Chip Enable : This active low input is used to enable the device and is sampled only when a new external address is loaded (ADV/LD LOW). This input can be used for memory depth expansion. | | 97 | 97 | CE2 | Synchronous Chip Enable : This active high input is used to enable the device and is sampled only when a new external address is loaded (ADV/LD LOW). This input can be used for memory depth expansion. | | 86 | 86 | OE | Output Enable : This active low asynchronous input enables the data l/0 0utput drivers. | | 85 | 85 | ADV/LD | Synchronous Address Advance/Load : When HIGH, this input is used to advance the internal burst counter, controlling burst access after the external address is loaded. When HIGH, R/W is ignored. A LOW on this pin permits a new address to be loaded at CLK rising edge. | | | | |
SY10H601JCTR on stock| | | | MIN. | TYP. | MAX. | | | LL | ICBO | VCB=-600 V, IF:=O | | | -10 | A | | -yL | IEBO - | VEB=-7.0 V, I(:=O | | | -10 | uA | | | hFFl | Vcr. = - 5.0 V, Ic = - 0.1 A | 30 | 58 | 120 | | | | hFE2 | VCF.= -5.0 V, Ic:= -0.5 A | 5 | 19 | | | | L | Vcs¨ | Ic=-0.3 A, IB=-0.06 A | | - 0.28 | - 0.5 | V | | - | VBr:(sat, | Ic=-0.3 A, IH=-0.06 A | | - 0.85 | -1.2 | V | | jU | C | VCB=-10 V, IF.=O, f-l.0 MHz | | 42 | 50 | pF | | | fT | VCFl=-10 V, If:.=0.1 A | 10 | 28 | | MHz | | - 7 7 | t(n | Ic=-O.5 A, RL=500 Q | | O1 | 0.5 | S | | | t stg | IHl = -IB2 = -0.1 A | | 3.5 | 5O | ZS | | | tf | Vcc:= -250 V | | 0.08 | 0.5 | us | | | | | | | |
As shown in the schematic diagram, the logic low bias cur- rent will flow until the PNP input is raised above the 3 diode reference (z 2.1V). Above this voltage the input device be- comes reverse biased and the input current drops to the leakage of the reverse biased junction0.1 yA).
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