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Note: 5. To accomplish internal initialization, CE and L-OEiRFSH are fixect at VIH for an interval of l ms when VcC reaches the specified volrage atter power is swiWied on. At least eighl dummy cycles must be executed tollowing that period. 6. Measured ai tT = 5 ns. 7. When measuring input signalliming, VIH (min) and VIL (max) are reference levels. a. Masured using an equivalem of loo pF and two standard l-TL loads. 9. LOE/RFSH inpullunctions as lower byte outpui enable input ( ) when CE = Viu and as refresTi input (RFSH ) when CE = VJH. 10. [CHZ and 10HZ are defined as the time until output enters lr:e open circuit state and the output vollage level becomes im m easurabla. 11. As with ordinary slatic RAM, write dala is incorporated at the rise of LWE, WE input or CE input, whichever is earlier. and write data is merefore held during tDSW, tDSC, tDHW, or tDHC. 12. Because address inpul is incorporated al the fall of CE,e add ress is m aintainad during tASC or tAHC. 13. After auto-rerresh has completed, CE must not be mada aclive unnl the tFCE period has elapsed.
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