SY3756G34B Datasheet| TA= 25IC | | | | | T=lMH | Z | | | | | | | | | | | | | | | | | | Rl | 95 | | | | | 2nd- | j | f | | | | ^J | | | | | | ___ _ | | | | | 2nd | | N | | | | 3rd | HL= 1UU | | | | | |
SY3756G34B Price| | TJrT | | | erxclk | In | 1 04MHz receive byte clock. The Core samples all Utopia Receive signals on rxclk rising edge. | | erxdata[31:0] | Out | Receive data bus. | | erxprty (0) | Out | Receive data bus parity. Standard odd or non standard even parity can be optionally generated by the Utopia Slave Core. When the parity generation is disabled during the Core configuration, the pin rxprty can be let unconnected. | | erxsoc | Out | Receive start of cell. Asserted to indicate that the current word is the first word of a cell. | | erxenb | ln | Active low transmit data transfer enable. | | erxclav[0] | Out | Cell buffer available. Asserted in octet level transfers to indicate to the Master that the FIFO is almost empty (Active low) or, in cell level transfers, to indicate to the Master that the PHY port FIFO has space one cell available in the FIFO. | | rxclav[3:1] (0) | Out | Extra FIFO Full/ Cell buffer available. In MPHY mode and when direct status indication is selected, one rxclav signal is implemented per PHY port. The maximum number of clav signals is limited to four. | | erxaddr(4:0) | In | Utopia receive address. When the Core operates in MPHY mode, address bus used during polling and slave port selection. Bit 4 is the MSB. taddr(4:0) becomes optional (And should be left open) when the Core does not operate in MPHY mode. | | | |
SY3756G34B on stock When the LTC1732 is in charge mode, the ~HR~ pin is pulled low by the internal N-channel MOSFET. To detect this mode, force the digital output pin, OUT, high and measure the voltage at the CHRG pin. The N-channel MOSFET will pull the pin low even with a 2k pull-up resistor. Once the charge current drops t0 10% of the full- scale current (C/lO),the N-channel MOSFET is turned off and a 35ad\ current source is connected to the CHRG pin. The IN pin will then be pulled high by the 2k pull-up. By | Features . Devices QML Qualified in Accordance with MIL-PRFF-38535 . Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96713 and Intersil's QM Plan . 1.25 Micron Radiation Hardened SOS CMOS . Single Event Upset (SEU) Immunity: <1 x 10.10 Errors/Bit/Day (Typ) * SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm2/mg . Dose Rate Upset . . . . . . . . . . . . . . . . >1011 RAD (Si)/s, 20ns Pulse . Dose Rate Survivability. . . . . . . . . . . >1012 RAD (Si)/s, 20ns Pulse | Pinouts 14 PIN Cl MIL-STD-183! R1 [ CP1 GND [ | -RAMIC DUAl i DESIGNATO .EAD FINISH ( TOP VIEW -u- | IN-LINE } CDIP2-T14 vcc D2 CP2 Q2 | | . Latch-Up Free Under Any Conditions . Military Temperature Range . . . . . . . . . . . . . . . . . . -55aC to +1250C . Significant Power Reduction Compared to ALSTTL Logic . DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V t0 5.5V . Input Logic Levels | 14 PIN CERAMIC FLATPACK MIL-STD-1835 DESIGNATOR CDFP3-F14, LEAD FINISH C TOP VIEW | | - VIL = 0.8V Max - VIH = VCC/2 Min . Input Current " 1.oA at VOL, VOH . Fast Propagation Delay. . . . . . . . . . . . . . . . 20ns (Max), 13ns (Typ) Description The Intersil ACTS74MS is a Radiation Hardened Dual D Flip Flop with | R1= D1[=2== CP12== S12== oi[=2= GND[== | 14 13 12 4 11 5 10 9 8 | =2 vcc =2 CP2 | | Set(s) and Reset (R). The logic level at data input is transferred to the output during the positive transition of the clock. The Set and Reset are independent from the clock and accomplished by a low level on the appropriate input. The ACTS74MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of a radiation hardened, high-speed, CMOS/SOS Logic Family. The ACTS74MS is supplied in a 14 lead Ceramic Flatpack (K suffix) or a 14 Lead Ceramic Dual-In-Line Package (D suffix). | | | Ordering Information | | | PART NUMBER | TEMPERATURE RANGE | SCREENING LEVEL | PACKAGE | | | 5962F9671301VCC | -550C to +1250C | MIL-PRF-38535 Class V | 14 Lead SBDIP | | 5962F9671301VXC | -550C to +1250C | MIL-PRF-38535 Class V | 14 Lead Ceramic Flatpack | | ACTS74D/Sample | 250C | Sample | 14 Lead SBDIP | | ACTS74K/Sample | 250C | Sample | 14 Lead Ceramic Flatpack | | ACTS74HMSR | 250C | Die | Die | | | | | | | | | | | |
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