| Parameter | KFMIG16Q2M Symbol Unit Min Max |
| Clock Clock Cycle | CLK 1 54 MHz tCLK 18.5 ns |
| Initial Access Time | tIAA 76 nS |
| Burst Access Time Valid Clock to Output Delay AVD Setup Time to CLK | tBA 14.5 ns tAVDS 7 ns |
| AVD Hold Time from CLK | tAVDH 7 nS |
| AVD High to OE Low Address Setup Time to CLK | tAVD0 0 ns tACS 7 ns |
| Address Hold Time from CLK | tACH 9 nS |
| Data Hold Time from Next Clock Cycle | tBDH 4 nS |
| Output Enable to Data | tOE 20 nS |
| CE Disable to Output High Z | tCEZl) 20 nS |
| OE Disable to Output High Z | tOEZl) 17 nS |
| CE Setup Time to CLK CLK High or Low Time | tCES 7 ns tCLKH/L tCLK/3 ns |
| CLK 2) to RDY valid | tRDY0 14 5 nS |
| CLK to RDY Setup Time RDY Setup Time to CLK | tRDYA 14.5 ns tRDYS 4 ns |
| CE low to RDY valid | tCER 15 nS |
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