| Pin | unction | Description | Interface Schematic |
| 1 | VCC1 | Supply voltage for the LNA. External RF and IF bypassing is required. The trace length between the pin and the bypass capacitors should be minimized. The ground side of the bypass capacitors should connect immediately to ground plane. | |
| 2 | GND | Ground connection. Keep traces physically short and connect immedi- ately to ground plane for best performance. | |
| 3 | LNAIN | RF input pin. This pin is internally DC blocked and matched t0 50 I . | vcc, ~O LNA OUT LNAIN O~ |
| 4 | GND | Same as pin 2 | |
| 5 | IF2 | FM IF output pin. This is a sjngle-ended output with an output imped- ance set by an internal 850 I resistor to Vcc. The resistor sets the operating impedance, but an external choke or matching inductor to Vcc must be supplied in order to correctly bias this output. This induc- tor is typically incorporated in the matching network between the output and IF filter. Because this pin is biased to Vcc, a DC blocking capacitor must be used if the IF filter input has a DC path to ground. | IF2 Vcc |
| 6 | GND | Same as pin 2 | |
| 7 | IF SELECT | Selects which IF output (IFl or IF2) is used. This is a digitally controlled input. A logic "high" selects IFl. A logic "low" selects IF2. The threshold voltage is approximately l.3V. | IF SELECT |
| 8 | GND | Same as pin 2 | |
| 9 | IF l+ | CDMA IF output pin. This is a balanced output. The output impedance is set by an internal soo I resistor to Vcc. Thus the output impedance of each pin is 500 I , whereas the differential output impedance is 1 000 I . The resistor sets the operating impedance, but an external choke or matching inductor to Vcc must be supplied in order to cor- rectly bias this output. This inductor is typically incorporated in the matching network between the output and IF filter. Because this pin is biased to Vcc, a DC blocking capacitor must be used if the IF filter input has a DC path to ground. | IFl+ IF1 |
| 1 0 | IF l- | Same as pin 9 except complementary input. | See pin 9 |
| 1 1 | GC | Analog gain adjustment for both IF output buffer amplifiers. A 10 k I source impedance is required for proper operation of the gain control circuitry. Valid control voltages, on the source side of the 10 k I resistor, are from OV t0 2.9V. Minimum gain is selected with 2.4V t0 2.9V. Maxi- mum gain is selected with OV t0 0.2V. When operating the RF9906 at fixed maximum gain, this pin should be grounded through a 10 kl resistor. Do not connect this pin directly to ground (see Application Schematic for example). | |
| 12 | VCC2 | Supply Voltage for the Mixer, LO Buffer Amplifier, and IF Buffer Amplifi- ers. External RF and IF bypassing is required. The trace length between the pin and the bypass capacitors should be minimized. The ground side of the bypass capacitors should connect immediately to ground plane. | |
| 1 3 | LO IN+ | Mixer LO Balanced Input Pin. This pin is internally DC biased and should be DC blocked if connected to a device with DC present. For single-ended input operation, one pin is used as an input and the other mixer LO input is AC coupled to ground. The single-ended input imped- ance is 50 I . | LO IN+ LO IN- |
| 14 | LO IN- | Same as pin 13, except complementary input. | See pin 13 |
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