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s SRAM No Wait Read An SRAM NoWait Readisa ReadinstructiontoanexternaISRAM that can be pipelined within a se ries ofoperations and does not require the user to wait forthe Read to complete before loading the nextinstruction. s DuaIWrite In addition to individual writes, the NSE has the ability to perform simultaneous writes to a Data entry and a respective external SRAM location. s Lookup Alookup can be req uested in 72-bit, 144-bit, 288-bit or 576-bit widths. A36-bitlookup can be accomplished by using two GlobaIMask Registers. s Learn The NSE implements a fully autonomous Learn Instruction, which providesa mechanism forthe usertowritealookupentry intoan unused location in the N SE and the associated data in exte rnal SRAM. This allows the userto update an entry into the NSE which had not previously been stored. The Learn writes the new entry, making it available for future lookups. SRAM Interface The NSE provides all required address and control signals for a gluelessSRAM interface. The NSE providesa pipelined bypasspathfor reads or writes to the external SRAM. The ASIC/FPGA handles the pipelining ofthe data toand from the SRAM.
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