| 28 | Row active to row active min | O | O | O | O | 1 | 1 | 1 | 1 | OFH | 15ns |
| 29 | /RAS to /CAS delay min (-7A/7AL) | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | OFH | 15ns |
| (-75/75L) | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 14H | 20ns |
| 30 | Minimum /RAS pulse width | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 2DH | 45ns |
| 31 | Density of each bank on module | 0 | 1 | 0 | 0 | 0 | 0 | 0 | O | 40H | 256MB |
| 32 | Address and command signalinput setup time | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 15H | 1.5ns |
| 33 | Address and command signalinput hold time | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 08H | 0.8ns |
| 34 | Data signal input setup time | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 15H | 1.5ns |
| 35 | Data signal input hold time | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 08H | 0.8ns |
| 36 t0 61 | Superset information | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | OOH | |
| 62 | SPD data revision code | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 12H | 1.2 |
| 63 | Checksum for Bytes o t0 62 (-7A/7AL) | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 92H | |
| (-75/75L) | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | D3H | |
| 64 t0 65 | Manufacturer's JEDEC ID code | O | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 7FH | Continuation code |
| 66 | Manufacturer's JEDEC ID code | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | FEH | Elpida Memory |
| 67 t0 71 | Manufacturer's JEDEC ID code | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | OOH | |
| 72 | Manufacturing location | | | | | | | | | | |
| | | | | | | | | | | |