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GENERAL DESCRIPTION The K78323625M and K78321825M are 37,748,736-bit Syn- chronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as lM(2M) words of 36(18) bits and integrates address and control registers, a 2-bit burst address counter and added some new functions for high performance cache RAM applications; W, BW, LBO, ZZ. Write cycles are internally self- timed and synchronous. Full bus~width write is done by~W, and each byte write is per- formed by the combination of WEx and BW when W is high. And with CSi high, ADSP is blocked to control signals. Burst cycle can be initiated with either the address status pro- cessor(ADSP) or address status cache controller(ADSC) inputs. Subsequent burst addresses are generated internally in the system's burst sequence and are controlled by the burst address advance~D /) input. LBO pin is DC operated and determines burst sequence(linear or interleaved). ZZ pin controls Power Down State and reduces Stand-by cur- rent regardless of CLK. The K78323625M and K78321825M are fabricated using SAM- SUNGs high performance CMOS technology and is available in a 100pin TQFP package. Multiple power and ground pins are utilized to minimize ground bounce.