| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact |
TPS71533QDCKRQ1G4 Datasheet
TPS71533QDCKRQ1G4 Price o ) 6 r - 6 6 3 r - - \ r : c o c \ ! C N O ) 3 r - r - o o r - 6 L O ( D 4 3 3 ( D ( D 6 O O ( D O C 0 6 0 3 r - - c x ] r - - c o L O O 0 2 5 0 0 . t r - o C 0 5 0 0 . t 6 0 ) 2 7 6 c o L 0 4 3 2 C N . - I I I 1 1 C N C N C O 0 0 0 4 4 4 4 L O i i i i i i i i i i T T T T i TPS71533QDCKRQ1G4 on stock
The K9F2808UOA is a 132Mbit(138,4'12,032 bit) memory organized as 32,768 rows(pages) by 528 columns. Spare sixteen columns are located from column address of 512 t0 527. A 528-byte data register is connected to memory cell arrays accommodating data transfer between the l/0 buffers and memory during page read and page program operations. The memory array is made up of 16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 32 pages formed by one NAND structures, totaling 8448 NAND structures of 16 cells. The array organization is shown in Figure 2. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 1024 separately erasable 16K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9F2808UOA. |
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