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MICROPROCESSOR INTERFACING Interfacing the DAC88 t0 8, 12 and 16-bit microprocessors is simplified by the DAC88's interna1 12-bit register. External address and control decoding will be required, however. Interfacing t0 12 and 10-bit processors is fairly direct and can usually be accomplished by NANDing the desired address lines with the processor's MEMORY WRITE orl/0 WRITEline and using the out- put to drive the DAC88's Register Enable input. For most processors, valid data remains on the data bus for a period of time after the removal of either valid address orcontrol signals. This results in data beinglatchedinto the DAC88 immediately afler one of the address or control signals changes but before valid data goes away. Interfacing t0 8-bit processors is slightly more complicated and an 8-bit external register is needed as shown in the sketch below. Address decoding must be organized such that the 8-bit in- termediate register and the DAC88's interna1 12-bit register appear at two different addresses. The 12 bits of digitaldata are sent to the DAC88 via two data transfers. First, the 8 least significant bits of digital data are written to the intermediate latch. Then, the 4 most significant bits of digital data are written to the DAC88's 12-bit latch. The resultis that the 4 MSB's on thedata bus and the 8 LSB's held in the intermediate latch are all latched into the DAC88's latch simultaneously. This technique is called double bufiering and it avoids the analog output slewing to an undesirable state determined by the LSB's of the new digitaldata and the MSB's of the previous digital data.
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