| Bit | @Pup | Name | Description |
| 7 | 1 | SRC[T/C]5 | SRC[T/C]5 0utput Enable 0 = Disable (Hi-Z), 1 = Enable |
| 6 | 1 | SRC[T/C]4 | SRC[T/C]4 0utput Enable 0 = Disable (Hi-Z), 1 = Enable |
| 5 | 1 | SRC[T/C]3 | SRC[T/C]3 0utput Enable 0 = Disable (Hi-Z), 1 = Enable |
| 4 | 1 | SRC[T/C]2 | SRC[T/C]2 0utput Enable 0 = Disable (Hi-Z), 1 = Enable |
| 3 | 1 | SRC[T/C]1 | SRC[T/C]1 0utput Enable 0 = Disable (Hi-Z), 1 = Enable |
| 2 | 1 | SRC [T/C]O | SRC[T/C]O Output Enable 0 = Disable (Hi-Z), 1 = Enable |
| 1 | 1 | SRCS[T/C]1 | SRCS[T/C]1 0utput Enable 0 = Disable (Hi-Z), 1 = Enable |
| 0 | 1 | SRCS[T/C]O | SRCS[T/C]O Output Enable 0 = Disable (Hi-Z), 1 = Enable |
| | | |
