TPS7350QPWLE Datasheet| | IIIII \/1tl - R(l(lrnA I narJ | | | /1-40 | c | | | | | | V | 5= | 70m | A LJ | )ad | | | | | 25 | c | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | N | --_ | 1 -_ | 25( | | | | | | | | | f | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
TPS7350QPWLE Price The output of the Tl bias winding is rectified and filtered by D3, Rl, and C5. The voltage across C5 is regulated by Ul, and is determined by the 5.7 V internal shunt regulator at the CONTROL pin of Ul. When the rectified bias voltage on C5 begins to exceed the shunt regulator voltage, TPS7350QPWLE on stock| | | | Limits | | | Symbol | Parameter | Test conditions | Min | Typ | Max | Unit | | V (BR) DSS | Drain-source breakdown voltage | ID = 1mA, VGs = OV | 100 | | | v | | IGSS | Gate-source leakage current | VGS = +20V, VDS = OV | | | ±0 1 | | | IDSS | Drain-source leakage current | VDS = 100V, VGS = OV | | | 0 1 | mA | | VGS (th) | Gate-source threshold voltage | ID = 1rriA, VDS = 10V | 1 0 | 1.5 | 2.0 | V | | rDS (ON) | Drain-source on-state resistance | ID = 25A, VGS = 10V | | 37 | 48 | m | | rDS (ON) | Drain-source on-state resistance | ID = 25A, VGS = 4V | | 40 | 52 | m | | VDS (ON) | Drain-source on-state voltage | ID = 25A, VGS = 10V | | 0 93 | 1 20 | V | | yfs | Forward transfer admittance | ID = 25A, VDS = 10V | | 40 | | S | | Ciss | Input capacitance | | | 3000 | | pF | | Coss | Output capacitance | VDS = 10V, VGS = Oy f= 1MHz | | 410 | | pF | | Crss | Reverse transfer capacitance | | 210 | | pF | | td (on) | Turn-on delay time | | | 22 | | ns | | tr | Rise time | VDD = 50y ID = 25A, VGS = 10V, RGEN = RGS = sol | | 65 | | ns | | td (off) | Turn-off delay time | | 270 | | ns | | | Fall time | | 160 | | ns | | VSD | Source-drain voltage | Is = 25A, VGS = OV | | 1.0 | 1.5 | V | | Rth (ch-c) | Thermal resistance | Channel to case | | | 1 78 | IC/W | | trr | Reverse recovery time | Is = 50A, dis/dt = -100A/c6 | | 90 | | ns | | | | | | | |
Memory Operation The FM24CL04 is designed to operate in a manner very similar to other 2-wire interface memory products. The major differences result from the higher performance write capability of FRAM technology. These improvements result in some differences between the FM24CL04 and a similar configuration EEPROM during writes. The complete operation for both writes and reads is explained below.
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