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This circuit divides the external clock frequency down to the switching frequency of the low pass and high pass switched capacitor filters. The divider also contains a TTL-CMOS in- terface circuit which converts the external TTL clock level to the CMOS logic level required for the divider logic. This in- terface circuit can also be directly driven by CMOS logic. A frequency select circuit is provided to allow the filter to oper- ate with 2.048 MHz, 1.544 MHz or l.536 MHz clock frequen- cies. By connecting the frequency select pin CLKO (pin 14) to Vcc, a 2.048 MHz clock input frequency is selected. Digi- tal ground selects l.544 MHz and VBB selects l.536 MHz.