Input voltage amplitude: 0.4 V t0 2.8 V Clock in_put voltage amplitude: 0.4V to Vcc-0.6V Input signal rise and fall time: 10 ns lnput judge level: 0.8 V and 2.0 V OOutput judge level: 0.8 V and 2.0 V Output load: ITTL + 100 pF (unless other+ wise specified)
TPS79633KTTTG3 on stock In addition to polynomial selection there are four other ca- pabilities provided for in the 'F402 ROM. The first is set or clear selectability. The sixteen internal registers have the capability to be either set or cleared when P is brought LOW. This set or clear capability is done in four groups of 4 (see Table lI, PO-P3). The second ROM capability (Co) is in determining the polarity of the check word. As is the case with the Ethernet polynomial the check word can be invert- ed when it is appended to the data stream or as is the case with the other polynomials, the residue is appended with no inversion. Thirdly, the ROM contains a bit (Ci) which is used to select the RFB input instead of the SEI input to be fed into the LSB. This is used when the polynomial selected is actually a residue (least significant) stored in the ROM which indicates whether the selected location is a polynomi- al or a residue. If the latter, then it inhibits the RFB input.
| UNIT | A | Ai max | bp | b1 | c | D | E | e | e1 | HE | Lp | Q | v | W | y |
| mm | 1 1 0 9 | 0 1 | 0 48 0 38 | 0 88 0 78 | 0 15 0 09 | 3 0 2 8 | 1 4 1 2 | 1 9 | 1 7 | 2 5 2 1 | 0 55 0 25 | 0 45 0 25 | 0 2 | 0 1 | 0 1 |
| | | | | | | | | | | | | | | |
