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TPSC476M010R0350- Datasheet
In addition to the basic integrate and deintegrate dual- slope phases discussed above, the TC820 design incorpo- rates a "zero integrator output" phase and an "auto-zero" phase. These additional phases ensure that the integrator starts at OV (even after a severe overrange conversion ,and that all offset voltage errors (buffer amplifier, integrator and
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In addition to lower switching frequency, the LT1 374 also operates at lower switch current limit when the feedback pin voltage drops belowl.7V. Q2 in Figure 2 pe rforms this function by clamping the Vc pin to a voltage less than its normal 2.1V upper clamp level. This foldbackcurrentlirnit greatly reduces power dissipation in the lC, diode and inductorduring short-circuit conditions. External synchro- nization is also disabled to prevent interference with foldback operation. Again, it is nearly transparent to the user undernormalload conditions.The onlyloadsthat may be affected are current source loads which maintain full load currentwith outputvoltagelessthan 50% offinalvalue. In these rare situations the feedback pin can be clamped above l.5V with an external diode to defeat foldback cur- rent limit. Caution:clamping the feedback pin means that frequency shifting will also be defeated, so a combination of high input voltage and dead shorted output may cause the LT1374 to lose control of current limit.
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Parameter Symbol Test Conditions Min Typ Max U nits
Power Good Threshold VPG VDRAIN - VEE, High to Low transition 1.5 1.75 2.0 V
Power Good Threshold Hysteresis VPGHY 0.4 V
Drain Input Bias Current ID RAIN VDRAIN 2 48V 1 5 50 pA
Output Low Voltage VOL SC4250H, VOL = PWRGD - VDRAIN @ VDRAIN = 5V, 10 = 1mA 1 V
SC4250L, VOL = PWRGD - VEE @ VDRAIN = 1V, 10 = 1mA 1 V
Output Leakage IOH SC4250H, VDRAIN -VEE = 1V, VPWRGD = 80V 1.0 10 lJA
SC4250L, VDRAIN -VEE = 5V 1.0 10 pA
AC Characteristics
OV High to Gate Low tPHLOV 1.7 IJs
UV Low to Gate Low tPHLUV 1.5 LJs
OV Low to Gate High tPLHOV 5.5 LJs
UV Low to Gate High tPLHUV 6.5 LJs
SENSE High to Gate Low tPHLSENSE 3 IJs
DRAIN Low to PWRGD Low DRAIN Low to (PWRGD - DRAIN) High tPHLPG 0.5 LJs
DRAIN High to PWRGD High DRAIN High to (PWRGD - DRAIN) Low tPLHPG O5 LJs
Gate ON Time - Time Delay tON_1 VDRAIN > 8V, after short circuit 5 LJs
Gate ON Time - Time Delay tON_2 VDRAIN < 7V, after short circuit 250 LJs


SYMBOL Rthjc MIN TYP MAX 100 UNIT oC/W Thermal Resistance -Infinite Heat Sink
Rthja 400 oC/W Thermal Resistance - No Heat Sink
d P/d Tj -0.6 %/oC Temperature Coefficient - Optical Power
dA/d Tj 0.3 nm/oC Temperature Coefficient -Whvelength
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