TQ2H-L-9V Datasheet| Data sheet status | | Objective specification | This data sheet contains target or goal specifications for product development. | | Preliminary specification | This data sheet contains preliminary data; supplementary data may be published later. | | Product specification | This data sheet contains final product specifications. | | Limiting values | | Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. | | Application information | | Where application information is given, it is advisory and does not form part of the specification. | | | TQ2H-L-9V Price| CHARACTERISTICS | SYMBOL | CONDITlONS | DEVICE TYPES | GROUP A SUB GROUPS | LIMITS MIN MAX | UNITS | | SWITCHING CHARACTERISTICS | | CLK Pulse Width High | tCH | | All | 9 | 90 | ns | | CLK Pulse Width Low | tCL | | All | 9 | 120 | ns | | SRI Data to CLK Setup | tDS | | All | 9 | 40 | ns | | SRI Data to CLK Hold | tDH | | All | 9 | 80 | ns | | [ij Pulse Width | tLD | | All | 9 | 120 | ns | | LSB CLK to Load | tSL | | All | 9 | O | ns | | FOAD High to CLK | tLC | | All | 9 | 0 | ns | | POWER SUPPLY | | Positive Supply Range | VDD | VDD= 5V | | | 4 75 5.25 | V | | (Note 7) | VDD= 15V | All | 1.2.3 | 14.25 1575 | | | | All digitalinputs = VL or VH | | | 500 | | | Negative Supply Range | IDD | All digital inputs = OV or Voo | All | 1,2,3 | 100 | pA | | | | | | | | TQ2H-L-9V on stock DESCRIPTION 6 PORTS -UNLOADED 6 PORTS - ST- MM, LQADED 6 PORTS - ST-SMLOADED 8 PORTS -UNLOADED 8 PORTS - ST- MM, LQADED 8 PORTS - ST- SM, LOADED 8 PORTS - DUR_D( SC UNLOADED 8 PORTS - DUPLB(SC - MM, LOADED 8 PORTS - DUR_D( SC -SM.LOADED 6 PORT MTRJ - UNLOADED 6 PORT- MTRJ - LOADED | Symbol | Parameter | Test Conditions | Minimum | Typical | Maximum | Units | | fMAX | Output Frequency | | | | 700 | MHz | | tPD | Propagation Delay; NOTE 1 | PLL_SEL = OV, f i 700MHz | 3.0 | | 4.2 | ns | | tsk(o) | Output Skew; NOTE 4, 5 | PLL_SEL = OV | | | 20 | ps | | f(O) | Static Phase Offset; NOTE 2, 5 | PLL_SEL = 3.3V | -50 | 50 | 150 | ps | | tjit(cc) | Cycle-to-Cycle Jitter; NOTE 5, 6 | | | | 25 | ps | | tjit(e) | Phase Jitter; NOTE 3, 5, 6 | | | | +50 | ps | | tL | PLL Lock Time | | | | 1 | ms | | tR | Output Rise Time | 20% t0 80% @ 50MHz | 300 | | 700 | ps | | tF | Output Fall Time | 20% t0 80% @ 50MHz | 300 | | 700 | ps | | odc | Output Duty Cycle | | 47 | | 53 | % | | | | | | | | |