| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact |
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TR-70B10-PV3Z Datasheet Operating Frequency Information Operating frequency information for a typical device (Figure 3) is presented as a guide for estimating device performance for a specific application. Other typical frequency vs collector current (ICE) plots are possible using the information shown for a typical unit in Figures 5, 6, 7, 8, 9 and 11. The operating frequency plot (Figure 3) of a typical device shows fMAXl or fMAX2; whichever is smaller at each point. The information is based on measurements of a typical device and is bounded by the maximum rated junction temperature. TR-70B10-PV3Z Price Lowest power 64 macrocell CPLD 6.0 ns pin-to-pin logic delays System frequencies up t0 145 MHz 64 macrocells with l,500 usable gates Available in small footprint packages - 44-pin PLCC (36 user l/0 pins) - 44-pin VQFP (36 user l/0 pins) - 48-ball CS BGA (40 user l/0 pins) - 56-ball CP BGA (48 user l/0 pins) - 100-pin VQFP (68 user l/0 pins) Optimized for 3.3V systems - Ultra-Iow power operation - 5V tolerant l/0 pins with 3.3V core supply - Advanced 0.35 micron five layer metal EEPROM process - Fast Zero PowerTM (FZP) CMOS design technology Advanced system features - In-system programming - Input registers - Predictable timing model - Up t0 23 available clocks per function block - Excellent pin retention during design changes - Full IEEE Standard 1149.1 boundary-scan (JTAG) - Four global clocks - Eight product term control terms per function block Fast ISP programming times Port Enable pin for dual function of JTAG ISP pins 2.7V t0 3.6V supply voltage at industrial temperature range Programmable slew rate control per macrocell Security bit prevents unauthorized access Refer to XPLA3 family data sheet ( ) for architecture description Table 7: Icc vs. Frequency (Vcc = 3.3V, 250C) TR-70B10-PV3Z on stock
Figure 2 relates the output state of a back-biased sensor lC, with switching characteristics shown in Figure 1, to the target gear profile and position. Assume a north pole back-bias configuration (equivalent to a south pole at the face of the device). The motion of the gear produces a phase-shifted field at El and E2 (Figure 2(a; internal conditioning circuitry subtracts the fields at the two elements (Figure 2(b; this differential field is band-pass filtered to remove dc offset components and then fed into a Schmitt trigger; the Schmitt trigger switches the output transistor at the thresholds BOP and BRP. As shown (Figure 2(c, the lC output is LOW whenever sensor E1 sees a (ferrous) gear tooth and sensor E2 faces air. The output is HIGH when sensor El sees air and sensor E2 sees the ferrous target. |
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