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TR1-6125T1A Datasheet

~ Vertical power DMOS output stage . Low on-state resistance . Overload protection against over temperature ' Overload protection against short circuit load ' Latched overload protection reset by input ' 5 V logic compatible input leve ~ Control of power MOSFET and supply of overload protection circuits derived from input ' Lower operating input current permits direct drive by micro-controller ' ESD protection on input pin . Overvoltage clamping for turn off of inductive loads
TR1-6125T1A Price

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TR1-6125T1A on stock

No	NAME	FUNCTION
1-5	GND	Emitter Power Ground
6	GND	Control G round (')
7	Vcc	Logic Supply Voltage
8	BD	Base Darlington
9	INPUT	Logic Input Channel (Internal Pull Down)
1 0	FLAG	Diagnostic Output Signal (Open Emitter)
TAB	HVC	Primary Coil Output Driver (Open Collector)

The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.

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		Exact Matc