| | | ADS5272 | |
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNITS |
| DC ACCURACY No Missing Codes DNL Differential Nonlinearity INL Integral Nonlinearity Offset Error(l) Offset Temperature Coefficient Fixed Attenuation in Channel(2) Variable Attenuation in Channel(3} Gain Error(4) Gain Temperature Coefficient(sl | fIN = 5MHz fIN = 5MHz REFT - REFB | -0.9 -2.0 TBD TBD | Assured +0.5 +0.6 +0.2 14 1 +0.2 +1.0 44 | 0 9 2 0 TBD TBD | LSB LSB %FS ppm/oC %FS %FS %FS ppm/oC |
| POWER SUPPLY lcc Total Supply Current I(AVDD) Analog Supply Current I(LVDD) Digital Output Driver Supply Current Power Dissipation Power Down | VIN = FS, FIN = 5MHz VIN = FS, FIN = 5MHz VIN = FS, FIN = 5MHz, LVDS Int0 100Q Load Clock Running | | 302 TBD TBD 996 90 | TBD | mA mA mA mW mW |
| REFERENCE VOLTAGES VREFT Reference Top (internal) VREFB Reference Bottom (internal) VCM Common-Mode Voltage VCM Output Current(6l VREFT Reference Top (external) VREFB Reference Bottom (external) External Reference Input Current(7) | +50mV Change in Voltage | 1.95 0.95 1.45 1.875 | 2 0 1 0 1 5 +2 2 0 | 2.05 1.05 1.55 1.12 5 | mA mA |
| ANALOG INPUT Differential Input Capacitance Analog Input Common-Mode Range Differential Input Voltage Range Voltage Overload Recovery Time Input Bandwidth | Differential Input Signal at 4Vpp Recovery to Within l% of Code -3dBFS | 1 5 | 7 0 4 0 300 | /CM±0 05 2 02 | pF V VPP CLK Cycles MHz |
| DIGITAL DATA OUTPUTS Data Bit Rate | | 340 | | 780 | MBPS |
| SERIALINTERFACE SCLK Serial Clock Input Frequency VIN LOW Input Low Voltage VIN HIGH Input High Voltage Input Current Input Pin Capacitance | | 2 1 | ±10 5 0 | 20 0 6 VDD | MHz UA pF |
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