description	IC Z8 MCU OTP 2K 20SSOP
Technical/Catalog Information	Z86E0812HEC1903TR
Vendor	Zilog
Category	Integrated Circuits (ICs)
RoHS Status	RoHS Non-Compliant
Other Names	Z86E0812HEC1903TR Z86E0812HEC1903TR
Lead Free Status	Contains Lead
Packaging	Tape & Reel (TR)
Operating Temperature	-40°C ~ 105°C
Package / Case	20-SSOP
Speed	12MHz
Interface	-
Program Memory Size	2K x 8
RAM Size	125 x 8
Number of I /O	14
Controller Series	Z8 OTP
Oscillator Type	Internal
Program Memory Type	OTP
EEPROM Size	-
Core Processor	Z8
Data Converters	-
Core Size	8-Bit

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suppliers of Z86E0812HEC1903TR and PDF data of Z86E0812HEC1903TR

Part Numbert	Mfg	Packt	D/C	Descriptiont	Qty	Company/Contact
Z86E0812HEC1903TR	Zilog	20-SSOP	00+/02+	NEW AND BLANK	1171	Fation Technology Limited Contact:Ashley Tel:86-755-83741448 Fax:86-755-83741449 Email: ashley@fationtech.com

Z86E0812HEC1903TR Datasheet


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Z86E0812HEC1903TR Price

Notes : I 1. All dimensions are m millimeters. 2. Tolerance is 0.10 mm unless otherwise noted.
Z86E0812HEC1903TR on stock

	INCH	MM
A	0.0433+ 0.004	l.10t O.10
Al	0.004+ 0.002	O.10f 0.05
A2	0.039+ 0.002	I.OO±0.05
b	0.009+ 0.002	0.77+ 0.05
bl	0.008+ 0.001	0.20+ 0.03
	0.0040.008	O.100.21
cl	0.0040.006	O.100.16
D	0.724+ 0.004	18AOt O.10
E	0.315+ 0.004	8.OOt O.10
c	0.020t 0.004	O.50t O.10
HD	0.787+ 0.008	20.00+ 0.20
L	0.0197 +000004	0.50 +00j
Ll	0.0315+ 0.004	0.80t O.10
y	0.004 Max	O.l Max
0	08'	08

8 t0 32K bytes ROM 256 bytes RAM 528 bytes full-screen display RAM 16-bit timer/counter . With 8-bit programmable prescaler . Can be split as tw0 8-bit timer/counters 14-bit base timer Watchdog timer (with external RC) Tw0 8-bit serial l/0 channels . One I2C bus serialinterface . One serial interface with baud rate generator Remote unit signal receive circuit 10-channel x 7-bit PWM outputs . Withstands up t0 15V 4-channel 4-bit /VD converter 20 110 ports, 8 input-only ports Numerous interrupt functions . 11 sources (5 external, 6 internal) and 9 vectors . Control function for 3 levels of overlapping interrupts Standby function (HALT/HOLD mode) High-speed operation . Minimum cycle time: 1 ys (bus cycle: 0.5 l_ts) . High-speed execution of register/RAM bit manipula- tion instructions: 1 pLS Symmetrical instruction set common with LC860000 Series . 68 instructions

Pin Number	Signal Name	Description
1	V3 3P	Main power input to the receiver. Input power requirements are defined in Table 3.
2	GND	DC ground to the receiver.
3	TX1	Primary asynchronous full-duplex serial data port transmit (TX) line. Binary and NMEA mes- sage protocols are supported. The default settings are: Message format Binary Baud 19200bps Parity None Data Bits 8 Stop Bit 1 For additional information, see the GPS receiver evaluation kit user manual.
4	RX1	Primary asynchronous full-duplex serial data port receive (RX) line. Binary and NM EA message protocols are supported. The default settings are: Message format Binary Baud 19200bps Parity None Data Bits 8 Stop Bit 1 For additional information, see the GPS receiver evaluation kit user manual.
5	TMARK	UTC time-mark pulse, one pulse per second. The Binary message OTMP contains the UTC time associated with the time-mark pulse.
6	V ANT	Provides a power connection to the center conductor of the RF connector.
7	V2 5BU	Provides a back-up power connection for the receiver's real time clock (RTC). Input power requirements are defined in Table 3.
8	RX2	Auxiliary asynchronous full-duplex serial data port receive (RX) line. DGPS RTCM SC-104 mes- sage protocol is supported. The default settings are: Message format RTCM SC-104 Baud 9600 Parity None Data Bits 8 Stop Bit 1 For additional information, see the GPS receiver evaluation kit user manual.

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